1. Field of the Invention
The present invention relates to a circuit for obtaining a bit synchronizing clock signal used for reproducing an EFM (eight to fourteen modulation) signal. More specifically, the present invention relates to an EFM signal frame period detecting circuit and a system for controlling the frequency of the bit synchronizing clock signal used for reproducing the EFM signal.
2. Description of Related Art
The EFM signal is prescribed in an international standard such as IEC908 and in a Japanese domestic standard such as JIS 8605 (1993), as a standard signal modulation system for recording a digital signal on a compact disk. In the EFM system, a source data is divided into units of 8 bits, and each unit of 8 bits is called a "symbol". The one symbol (composed of 8 bits) is converted into a signal composed of 14 bits, as shown in FIG. 1. At this time, each of 14 bits of the symbol is called a "channel bit". The signal composed of 14 channel bits is constructed in such a manner that a minimum interval between two adjacent bit inversions is 3 bits, and a maximum interval between two adjacent bit inversions is 11 bits. In addition, as shown in FIG. 1, one frame is constituted of 588 channel bits, and a frame synchronizing signal is inserted into each one frame. The frame synchronizing signal is constituted of a pulse signal having a high level duration of a 11-bit width and a low level duration of a 11-bit width adjacent to each other. At the time of reproducing the EFM signal, this frame synchronizing signal is detected for the purpose of controlling a producing velocity.
In the prior art, at the time of reproducing the EFM signal recorded in a compact disk or another in the form modulated in the EFM system, the frequency of the bit synchronizing clock signal used for reproducing the EFM signal is controlled as proposed by Japanese Patent Application Pre-examination Publication No. JP-A-58-056258 and its corresponding U.S. Pat. No. 4,532,561 claiming Convention Priorities based on four Japanese patent applications including the Japanese Patent Application No. Showa 56-153707 published as JP-A-58-056258 (the content of U.S. Pat. No. 4,532,561 is incorporated by reference in its entirety into this application). Namely, in order to detect the frame synchronizing signal defined to have a maximum pulse width of various components included in the EFM signal, a duration for detecting the frame synchronizing signal is set to a duration corresponding to four times a predetermined frame period, and a maximum pulse width is detected in each detecting duration. Then, a frame period is predicted from the detected maximum pulse width, and a rotating speed of the disk is controlled to put the predicted value within a predetermined range, so as to maintain a linear velocity of the signal at a constant value (this is generally called a "constant linear velocity (CLV) system"). Thus, the EFM signal is reproduced.
As mentioned above, when the EFM signal is reproduced in the prior art, the reproducing velocity is maintained at a predetermined velocity. For this purpose, however, since the duration for detecting the frame synchronizing signal is set to several times the predetermined frame period, a long time is required until the EFM signal is reproduced.